RESETting Timed Machines

Abstract

Many real-time applications enable RESET to account for all kinds of unexpected problems, or to accommodate for a users’ want of restarting. Additionally, some software testing techniques must allow for resetting timed-Implementations Under Test (t-IUT). Dedicated internal logic is probably the most common of solutions for accomplishing such tasks. There are situations, however, where such a privilege doesn’t exist; thus, it cannot be built upon. Testing pre-engineered timed-IUTs is one such case. In this paper we wish to present an algorithm for the direct generation of timed RESET sequences from the timed-IUT specification, such that it should be optimal w.r.t. to execution time.