Fast Packet Switches with Shared Buffer Memory

Abstract

Modern networks (such as BISDN, gigabit networks, parallel computer networks, LANs, etc.) introduce fast packet switches as a new concept of a switching node. Fast packet switches which employ shared storage are able to utilize the buffer efficiently. Several analytical techniques to evaluate the performance of shared buffer switches have been proposed. They range from the simple convolution technique which is fast but inaccurate, to the approach proposed by Eckberg and Hou, which is accurate, but computationally slow. This paper proposes a new approach to performance analysis of shared buffer switches, called the reduced variance approximation (RVA). The new method appears to offer accurate results and efficient computation in comparison to other approaches. Implementation of this method provides reduction in the required shared buffer size.